Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications.
One type of smaller packaging for semiconductor devices that has been developed is wafer level packaging (WLP), in which integrated circuit die are packaged in packages that typically include a post-passivation interconnect (PPI) structure or a redistribution layer (RDL) that is used to fan out wiring for contact pads of the integrated circuit die so that electrical contact can be made on a larger pitch or pad than contact pads of the die. WLP packages have been applied more and more in integrated circuit packaging due to the advantages of their simple structures. However, for some WLP packages, the under bump metallization (UBM) layers used in WLP packages can be costly. For some other low cost WLP packages without UBM layers, adhesion between connection devices such as solder balls and PPI structures can cause problems such as a higher incidence of ball cracks. The design of low cost WLP packages without UBM layers while increasing adhesion between connection devices such as solder balls and PPI structure is a challenge.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.